As computer hardware and software technology continues to progress, the need for larger and faster mass storage devices for storing computer software and data continues to increase. Electronic databases and computer applications such as multimedia applications require large amounts of disk storage space. An axiom in the computer industry is that there is no such thing as enough memory and disk storage space.
To meet these ever increasing demands, hard disk drives continue to evolve and advance. Some of the early disk drives had a maximum storage capacity of five megabytes and used fourteen inch platters, whereas today's hard disk drives are commonly over one gigabyte and use 3.5 inch platters. Correspondingly, advances in the amount of data stored per unit of area, or areal density, have dramatically accelerated. For example, in the 1980's, areal density increased about thirty percent per year while in the 1990's annual areal density increases have been around sixty percent. The cost per megabyte of a hard disk drive is inversely related to its areal density.
Mass storage device manufacturers strive to produce high speed hard disk drives with large data capacities at lower and lower costs. A high speed hard disk drive is one that can store and retrieve data at a fast rate. One aspect of increasing disk drive speed and capacity is to improve or increase the areal density as well as increases rotational speed. Areal density may be increased by improving the method of storing and retrieving data.
In general, mass storage devices and systems, such as hard disk drives, include a magnetic storage media, such as rotating disks or platters, a spindle motor, read/write heads, an actuator, a pre-amplifier, a read path, a write path (as traditionally part of the read channel), a servo controller or digital signal processor, and control circuitry to control the operation of the hard disk drive and to properly interface the hard disk drive to a host or system bus. The read path, write path, servo controller, and a memory might be implemented as one integrated circuit that is referred to as a data channel. The control circuitry often includes a microprocessor or digital signal processor (DSP) for executing control programs or instructions during the operation of the hard disk drive.
A hard disk drive performs write and read operations when storing and retrieving data. A typical hard disk drive performs a write operation by transferring data from a host interface to its control circuitry. The control circuitry then stores the data in a local dynamic random access memory. A control circuitry processor schedules a series of events to allow the information to be transferred to the disk platters through a write channel. The control circuitry moves the read/write heads to the appropriate track and locates the appropriate sector of the track. Finally, the hard disk drive control circuitry transfers the data from the dynamic random access memory to the located sector of the disk platter through the write channel. A sector generally has a fixed data storage allocation, typically 512 bytes of user data. A preamble is provided before each sector and allows for the read/write head to adjust to the proper sampling scheme before reading the user data. A write clock controls the timing of a write operation in the write channel. The write channel may encode the data so that the data can be more reliably retrieved later.
In a read operation, the appropriate sector to be read is located by properly positioning the read head and data that has been previously written to the disk is read. The read/write head senses the changes in the magnetic flux of the disk platter and generates a corresponding analog read signal. The read channel receives the analog read signal, conditions the signal, and detects "zeros" and "ones" sequences from the signal. The read channel conditions the signal by amplifying the signal to an appropriate level using automatic gain control (AGC) techniques. The read channel then filters the signal, to eliminate unwanted high frequency noise, equalizes the samples to fit the particular spectrum, detects "zeros" and "ones" sequences from the signal, and formats the binary data for the control circuitry. The binary or digital data is then transferred from the read channel and is stored in the DRAM of the control circuitry. The processor then communicates to the host that data is ready to be transferred. A read clock controls the timing of a read operation in the read channel.
As the disk platters are moving, the read/write heads must align or stay on a particular track. This is accomplished by reading auxiliary information from the disk called a servo wedge. The servo wedge indicates the position of the heads both in a radial direction and along the circumference of a track. The data channel receives this position information so the servo controller can continue to properly position the heads on the track.
In modern disk drives the PRML scheme is the most popular detection scheme. PRML is an acronym for Partial Response Maximum Likelihood. PRML detection consist of a maximum likelihood detector of a partial response coding method.
A first generation of PRML channels was equalized using a PR4 response. PR4 stands for Class IV partial response and is a way to model the pulse shape of the sampled signal. However, at current recording channel densities, frequency response of the magnetic recording channel closely resembles an extended partial response class 4 (EPR4) channel response. The discrete-time impulse response transfer function of an EPR4 channel is 1+D-D.sup.2 -D.sup.3, where "D" =e.sup.-j.omega.T, where ".omega." is a frequency variable in radians per second and "T" is the sampling time interval in seconds. An EPR4 channel has more low frequency and less high frequency content than a PR4 channel. Therefore, modeling a magnetic recording channel as an EPR4 response yields better performance at higher recording channel densities, since equalizing a magnetic recording channel to an EPR4 channel response results in less high frequency is noise enhancement.
An analog signal is provided to a read channel as described above. The read channel samples the preamble once per clock cycle. One of the purposes of acquiring the preamble signal is to synchronize the times at which samples are acquired from the analog signal. Data is stored in the analog signal according to an EPR4 controlled intersymbol interference scheme. It has been determined that sampling of these data values is optimum at particular times. Therefore, it is desirable to align sampling of the analog signal with the clock signal of the read channel so that sampling occurs at correct time periods. This alignment is often performed iteratively by components similar in operation to a phase lock loop.
In some implementations, the phase difference between the sampled analog signal and the clock signal that would provide optimum sampling is adjusted by estimating the difference between the phases of the sampled analog signal and the clock signal according to predetermined formulas based upon PR4 response. However, it has been determined that these equations do not lead to desirable correction of the phase differences of an EPR4 response system and have a stable false-locking operating point.